1. Field of the Invention
The invention relates generally to semiconductor memory devices and, more particularly, relates to a semiconductor memory device for storing a plurality of data on a word basis and an operating method thereof.
2. Description of the Background Art
FIG. 8 is a diagram showing one example of a conventional semiconductor memory device for storing a plurality of data on a word basis. This semiconductor memory device is disclosed in Japanese Patent Laying-Open No. 3-25793 and "1989 SPRING NATIONAL CONVENTION RECORD, THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS", PP. 5-304.
In this semiconductor memory device, data of one word is divided into a plurality of subwords, and control of input and output for each subword is possible. In this example, one word includes input data DI0-DI15 of 16 bits or output data DO0-DO15, and one word is divided into four subwords SW0-SW3. The subword SW0 includes input data DI0-DI3 of 4 bits or output data DO0-DO3 of 4 bits. The subwords SW1, SW2, SW3 also include input data of 4 bits or output data of 4 bits. That is, suppose k=0, 1, 2, 3, a subword SWk includes input data DI (4k)-DI (4k+3) or output data DO (4k)-DO (4k+3).
In FIG. 8, a bit line load device 2, a column selection circuit 3 and an addressing device 4 are connected to a memory cell array 1. A detailed configuration of the memory cell array is shown in FIG. 9. Referring to FIG. 9, a plurality of word lines WL and a plurality of bit line pairs BL, BL are arranged to cross each other with memory cells MC provided at their cross-over points. Each memory cell MC includes two inverters G21, G22 constituting a latch circuit and N channel MOS transistors Q71, Q72.
The addressing device 4 in FIG. 8 includes a holding circuit 5 for holding N address signals AO-AN-1 which are externally applied and a decoder 6 for decoding and applying an address signal supplied from the holding circuit 5 to the memory cell array 1.
Referring back to FIG. 9, one of the plurality of word lines WL is selected, and 16 bit line pairs BL, BL corresponding to one word are selected in the plurality of bit line pairs BL, BL by the column selection circuit (FIG. 8) in response to the address signal decoded by the decoder 6 (FIG. 8).
A data input-output device 70, a write control device 8, a read control device 90 and an output control device 91 are provided in FIG. 8.
The data input-output device 70 includes 16 write circuits WC0-WC15, 16 data holding circuits DH0-DH15 and 16 output circuits OC0-OC15. The write circuits WC0 -WC3, the data holding circuits DH0-DH3 and the output circuits OC0-OC3 are provided corresponding to the subword SW0. Similarly, the write circuit WC (4k)-WC (4k+3), the data holding circuits DH (4k)-DH (4k+3) and the output circuits OC (4k)-OC (4k+3) are provided corresponding to a subword SWk, where k represents 0, 1, 2, 3.
The write control device 8 includes four 3-input NOR circuits G1-G4 corresponding to four subwords SW0-SW3. An externally applied chip enable signal CE is supplied to one input terminal of each of the NOR circuits G1-G4, and an externally applied write enable signal WE is supplied to the other one input terminal. Externally applied sub write enable signals SWE0-SWE3 are applied to the remaining input terminals of the NOR circuits G1-G4, respectively. The sub write enable signals SWE0-SWE3 respectively correspond to the subwords SW0-SW3. The output of the NOR circuit G1 is supplied to the control terminals of four corresponding write circuits WC0 -WC3. Similarly, the output of each of the NOR gates G2-G4 is supplied to the control terminals of four corresponding write circuits.
The externally applied input data DI0-DI15 is applied to the write circuits WC0-WC15 respectively. The data of one word (16 bits) read from the memory cell array 1 is held respectively in the data holding circuits DH0-DH15, and externally supplied through the output circuits OC0-OC15 as output data DO0-D015.
The read control device 90 includes a 2-input AND circuit. An inverted signal of the chip enable signal CE is supplied to one input terminal of the read control device 90, and the write enable signal WE is supplied to the other input terminal.
The output control device 91 includes four buffer circuits G11-G14 corresponding to four subwords SW0-SW3. Sub output enable signals SOE0-SOE3 are supplied to the input terminals of the buffer circuits G11-G14. The output of the buffer circuit G11 is supplied to the control terminals of four corresponding output circuits OC0-OC3 as an output control signal. Similarly, the output of each of the buffer circuits G11-G14 is respectively supplied to the control terminal of each of four corresponding output circuits as an output control signal.
The operation of writing data will now be described.
Suppose that the subword SW0 controlled by the sub write enable signal SWE0 is selected, and other subwords SW1-SW3 are not selected.
The chip enable signal CE is brought to an L level. This semiconductor memory device becomes capable of writing or reading data. 16 memory cells MC in which data is to be written in the memory cell array 1 are selected by address signals AO-AN-1.
When the write enable signal WE attains an L level, the output of the read control device 90 attains an L level. As a result, the data holding circuits DH0-DH15 provides high impedance outputs.
Furthermore, the sub write enable signal SWE0 attains an L level, and the remaining sub write enable signals SWE1-SWE3 remain at an H level. The output of the NOR circuit G1 attains an H level, and the outputs of the NOR circuits G2-G4 attain an L level. The write circuits WC0-WC3 are brought to an active state, and the remaining write circuits are put in an inactive state, so that it becomes possible to input the input data DI0-DI3 belonging to the subword SW0. The subword SW0 is therefore written in four corresponding memory cells MC in the 16 selected memory cells MC. At this time, writing of data is not effected in a memory cell MC corresponding to the subwords SW1-SW3 in the 16 selected memory cells MC.
The operation of reading data will now be described.
Suppose that the subword SW0 controlled by the sub output enable signal SOE0 is selected, and other subwords SW1-SW3 are not selected.
When the chip enable signal CE attains an L level, this semiconductor memory device becomes capable of writing or reading data. 16 memory cells MC in which data is to be read in the memory cell array 1 are selected by address signals AO-AN-1.
When the write enable signal WE attains an H level, the outputs of the NOR circuits G1-G4 attain an L level regardless of the state of the sub write enable signals SWE0-SWE3. The outputs of the write circuits WC0-WC15 are brought to a high impedance state.
The output of the read control device 90 attains an H level, and the data holding circuits DH0-DH15 are brought to an active state. As a result, the data of one word read from the memory cell array 1 is held in the data holding circuits DH0-DH15.
The sub output enable signal SOE0 attains an L level, and the sub output enable signals SOE1-SOE3 remain at an H level. The output control signal supplied from the buffer circuit G11 attains an H level, and the output control signals supplied from other buffer circuits G12-G14 attain an L level. As a result, four output circuits OC0-OC3 corresponding to the subword SW0 are brought to an active state, and the remaining output circuits are put in an inactive state. The data held in the data holding circuits DH0-DH3 is externally supplied through the output circuits OC0-OC3 as output data DO0-DO3. Data held in the data holding circuits corresponding to the subwords SW1-SW3 is not outputted.
As stated above, any subword in externally applied data of one word can be written in the memory cell array 1, and any subword in data of one word stored in the memory cell array 1 can be externally read.
In the semiconductor memory device above, however, when data of one word is read from the memory cell array 1, data of one word which has been held in the data holding circuits DH0-DH15 is rewritten with the read data of one word. That is, when new data of one word is read from the memory cell array 1 after any subword in the plurality of subwords held in the data holding circuits DH0-DH15 is externally read, the subword which was not externally read in the plurality of subwords held in the data holding circuits DH0-DH15 is also rewritten with the new data.
Therefore, it is impossible to generate in the device new data including a subword contained in some one word and a subword contained in other word.
With diversification of a system, it is thought that the scope of application of a semiconductor memory device can be expanded if a subword contained in some one word and a subword contained in other word can be combined together in a device.